XMC with user configurable Kintex-7 FPGA, 24 ADC input ch.

SKU:
TXMC638
Fabrikant:
Tews
  • I/O Type : Analog I/O
  • Type Mezzanine : XMC

Tews TXMC638 Reconfigurable FPGA with 24 x 16 bit Analog Input
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Détails
Spécifications
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Tews User Programmable FPGA on a XMC Module

The TXMC638 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable Xilinx Kintex-7 FPGA with 24 ADC input channel.

The TXMC638 provides 24 ADC input channels based on the Linear Dual 16-Bit 5Msps Differential LTC2323-16 ADC. Each of the 24 channels has a resolution of 16bit and can work with up to 5Msps. The analog input circuit is designed to allow input voltages up to ±2.5 V on each input-pin (results in ±5 V differential voltage range).

For customer specific I/O extension or inter-board communication, the TXMC638 provides 64 FPGA I/Os on P14 and 4 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines can be configured as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface.

Additionally the TXMC638 provides three 100 Ohm terminated ac-coupled, differential inputs with wide Input voltage range.

The User FPGA is connected to a 1GB, 32 bit wide DDR3 SDRAM. The SDRAM-interface uses an internal Memory Controller of the Kintex-7.

The User FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies “Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design by using the Xilinx Vivado Logic Analyzer.

User applications for the TXMC638 with Kintex-7 FPGA can be developed using the Xilinx design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required.
Spécifications
  • Caractéristiques principales
    caractéristiques• User configurable Xilinx Kintex-7 FPGA with 24 ADC input channel
    • 24 ADC input channels based on the Linear Dual 16-Bit 5Msps
    • The analog input circuit is designed to allow input voltages up to ±2.5 V on each input-pin (results in ±5 V differential voltage range)
    • 64 FPGA I/Os on P14 and 4 FPGA Multi-Gigabit-Transceiver on P16 for customer specific I/O extension or inter-board communication
  • Spécifications mécaniques
    Type MezzanineXMC
  • Spécifications électriques
    plage d'entrée3.0 A, typical @ +5V VPWR & 1.25 A, typical @ +12V VPWR (Depends on FPGA design With TXMC638 Board Reference Design / without external load)
  • Spécification environnementale
    température de stockage-40°C to +85°C
    température de fonctionnement-40°C/+85°C
    humidité relative5 – 95 % non-condensing
  • Certificats
    certificatsRoHS Compliant
    • TXMC638-10R Kintex-7 FPGA XC7K160T-2 FBG676, 1GBDDR3 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16
    • TXMC638-11R Kintex-7 FPGA XC7K325T-2 FBG676, 1GBDDR3 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16
    • TXMC638-12R Kintex-7 FPGA XC7K410T-2 FBG676, 1GBDDR3 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16
  • Données GENERALES
    FabricantTews
    Garantie60 Maanden
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