PCIe module with User-Programmable Kintex-7 FPGA, 16 ADC/DAC

  • Type I/O : Analoge I/O
  • Type Opsteekkaart : pci-e

Tews TPCE636 Reconfigurable FPGA with 16x 16bit Analog Input and 16x 16bit Analog Output
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Tews PCIe module with Xilinx FPGA for Analog I/O

The TPCE636 is a half-length X4 PCIe compatible module providing a user configurable Kintex7 FPGA with 16 ADC input channels and 16 DAC output channels.

The TPCE636 ADC input channels are based on the Linear Dual 16-Bit 5Msps Differential LTC2323-16 ADC. The TPCE636 provides 16 ADC channels. Each of the 16 channels has a resolution of 16bit and can work with up to 5Msps. The analog input circuit is designed to allow input voltages up to ±10V on each input-pin (results in ±20V differential voltage range).

The TPCE636 DAC output channels are based on the Dual 16bit AD5547 DAC. Each DAC output is designed as a single-ended bipolar ±10V analog output.

For customer specific I/O extension or inter-board communication, the TPCE636 provides 64 FPGA I/Os on a back I/O connector and 4 FPGA Multi-Gigabit-Transceiver on a Samtec FireFly© connector. Digital back I/O lines can be configured as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface.

All front I/O lines such as the ADC interface and DAC interface are connected to a 98-pin. Samtec ERF8-049 Rugged EdgeRate Connector.

The User FPGA is connected to a 1GB, 32 bit wide DDR3 SDRAM. The SDRAM-interface uses an internal Memory Controller of the Kintex-7.

The User FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies Tandem PROM should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx ChipScope).

User applications for the TPCE636 with Kintex-7 FPGA can be developed using the design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required.

TEWS offers a well-documented FPGA Board Reference Design. It includes constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the TPCE636.

The TPCE636 is delivered with the FPGA Board Reference Design. The user FPGA can be programmed via the on-board Board Configuration Controller (BCC). Programming via the JTAG interface using an XILINX USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation.
  • Belangrijkste eigenschappen
    Kenmerken• Form Factor: half-length X4 PCIe
    • PCI Express x4 Link (Base Specification 2.1)
    • Reconfigurable Kintex-7 FPGA
    • 16 differential analog inputs
    • 16 differential analog outputs
    • 64 single ended or 32 differential back I/O lines on a rear 68pin ERNI SMC connector
    • 4 FPGA Multi-Gigabit-Transceiver on a rear Samtec FireFly(c) connector.
    • Operating temperature -40°C to +85°C
  • Poorten & Interfaces
    Type I/OAnaloge I/O
  • Mechanische specificaties
    Type Opsteekkaartpci-e
  • Electrische specificaties
    Input rangetypical @ +3.3V PCIe
  • Omgeving specificatie
    Opslag temperatuur-40°C to +85°C
    Operating Temperatuur-40°C/+85°C
    Relatieve luchtvochtigheid5 – 95 % non-condensing
  • Certificeringen
    • TPCE636-xxR: 240000 h

    MTBF values shown are based on calculation according to MIL-HDBK-217F and MIL-HDBK-217F Notice 2; Environment: GB 20°C.

    The MTBF calculation is based on component FIT rates provided by the component suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
  • Generieke data
    Garantie60 Maanden

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