XMC module XCZU7EV Rear I/O conduction cooled

XMC-FZU Series: Configurable Zynq® UltraScale+TM MPSoC with Plug-In I/O Description

XMC-FZU series modules provide a programmable AMD Zynq UltraScale+ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. Two multi-core ARM Cortex CPUs (A53 application processor and R5 real-time processor) deliver high-performance computation capability. Additional resources include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The integrated ASIC-class programmable logic is ideal for compute-intensive tasks and offloading critical applications.

An AXM-FZU01 expansion I/O module with dual QSFP+ ports plugs in to interface high-speed signals, such as 10GbE, to the programmable logic. Other AXM mezzanine modules can support a variety of fiber optic or LVDS I/O interfaces.

The rear XMC connectors route peripheral I/O to the processor system and high-speed serial lanes for PCIe, Serial RapidIO or 10-Gigabit Ethernet. Additional user I/O such as high speed serial, LVDS or global clock signals can also access the programmable logic over the rear connectors.

The real value of the Zynq UltraScale+ MPSoC architecture lies in the tight integration of its programmable logic with the processing system. Its high throughput interface eliminates bottlenecks that plague two-chip ASSP-FPGA solutions and allows designers to easily extend the processing system capabilities. Now developers can build custom designs by adding peripherals in the programmable logic and increase overall system performance by partitioning hardware and software functions with custom accelerators.

Designed for COTS applications these MPSoC I/O modules deliver user-customizable I/O in a high-density and very rugged form factor. Typical applications involve adaptive filtering, sensor fusion, motor control, and image processing.

Acromag’s Engineering Design Kit (EDK) provides example designs that provides host access to the hardware I/O. The examples are implemented using the Xilinx Vivado® development environment and offer a starting point from which customers can develop their customized applications. Vitis® and PetaLinux® examples are also provided.